Final changes

CMakeLists.txt

@@ -23,14 +23,15 @@ set(CMAKE_CXX_STANDARD_REQUIRED ON)
 set(CMAKE_CXX_EXTENSIONS ON)
 
 set(MX_INCLUDE_DIRECTORIES
-    ${CMAKE_CURRENT_SOURCE_DIR}/Core/Include
-    ${CMAKE_CURRENT_SOURCE_DIR}/Core/Include/*
     ${CMAKE_CURRENT_SOURCE_DIR}/Drivers/CMSIS/Device/ST/${MCU_FAMILY}/Include
     ${CMAKE_CURRENT_SOURCE_DIR}/Drivers/CMSIS/Include
 )
 
 set(PROJECT_INCLUDE_DIRECTORIES
     ${CMAKE_CURRENT_SOURCE_DIR}
+    ${CMAKE_CURRENT_SOURCE_DIR}/Core/Include/Timer
+    ${CMAKE_CURRENT_SOURCE_DIR}/Core/Include/Timer/Reg
+    ${CMAKE_CURRENT_SOURCE_DIR}/Core/Include
 )
 
 file(GLOB_RECURSE PROJECT_SOURCES

Core/Include/Reg/SHAL_TIM_REG.h

@@ -1,12 +0,0 @@
-#ifndef SHAL_TIM_REG
-#define SHAL_TIM_REG
-
-
-#include "stm32f0xx.h"  // Or your device header
-
-enum class S_TIM{ //Sample
-    S_TIM_1 = 0xFFA0,
-    S_TIM_2 = 0xFF,
-};
-
-#endif

Core/Include/SHAL.h

@@ -8,7 +8,7 @@
 #ifndef SHAL_H
 #define SHAL_H
 
-
+#include "Core/Include/Timer/SHAL_TIM.h"
 
 
 #endif

Core/Include/SHAL_TIM.h

@@ -1,8 +0,0 @@
-#ifndef SHAL_TIM_H
-#define SHAL_TIM_H
-
-#include "SHAL_TIM_REG.h"
-
-
-
-#endif

Core/Include/Timer/Reg/SHAL_TIM_CALLBACK.h

@@ -0,0 +1,26 @@
+//
+// Created by Luca on 8/28/2025.
+//
+
+#ifndef SHMINGO_HAL_SHAL_TIM_CALLBACK_H
+#define SHMINGO_HAL_SHAL_TIM_CALLBACK_H
+
+#include "SHAL_TIM_REG.h"
+
+#define DEFINE_TIMER_IRQ(key, irq_handler)                \
+extern "C" void irq_handler(void) {                       \
+    auto tim_reg = getTimerRegister(key);                 \
+    if (tim_reg->SR & TIM_SR_UIF) {                       \
+        tim_reg->SR &= ~TIM_SR_UIF; /* clear flag */      \
+        auto cb = timer_callbacks[static_cast<int>(key)]; \
+        if (cb) cb();                                     \
+    };                                                    \
+};
+
+typedef void (*TimerCallback)(); //Typedef for callback function
+
+[[maybe_unused]] static TimerCallback timer_callbacks[static_cast<int>(Timer_Key::NUM_TIMERS)] = {nullptr}; //Timer IRQ Callback table
+
+void registerTimerCallback(Timer_Key key, TimerCallback callback);
+
+#endif //SHMINGO_HAL_SHAL_TIM_CALLBACK_H

Core/Include/Timer/Reg/SHAL_TIM_REG.h

@@ -0,0 +1,91 @@
+#ifndef SHAL_TIM_REG_H
+#define SHAL_TIM_REG_H
+
+#include <cstdint>
+#include <cassert>
+#include <stm32f072xb.h>
+
+
+enum class Bus {
+    AHB,
+    APB1,
+    APB2,
+    INVALID
+};
+
+struct RCC_Peripheral {
+    Bus bus;
+    volatile uint32_t* reg;
+    uint32_t bitmask;
+};
+
+enum class Timer_Key { //For STM32F072
+    S_TIM1,
+    S_TIM2,
+    S_TIM3,
+    S_TIM14,
+    S_TIM15,
+    S_TIM16,
+    S_TIM17,
+    NUM_TIMERS,
+    S_TIM_INVALID
+};
+
+
+//Get timer peripheral struct including bus register, enable mask, timer mask
+constexpr RCC_Peripheral getTimerRCC(Timer_Key t) {
+    switch(t) {
+        case Timer_Key::S_TIM1:  return {Bus::APB2, &RCC->APB2ENR, RCC_APB2ENR_TIM1EN};
+        case Timer_Key::S_TIM2:  return {Bus::APB1, &RCC->APB1ENR, RCC_APB1ENR_TIM2EN};
+        case Timer_Key::S_TIM3:  return {Bus::APB1, &RCC->APB1ENR, RCC_APB1ENR_TIM3EN};
+        case Timer_Key::S_TIM14: return {Bus::APB1, &RCC->APB1ENR, RCC_APB1ENR_TIM14EN};
+        case Timer_Key::S_TIM15: return {Bus::APB2, &RCC->APB2ENR, RCC_APB2ENR_TIM15EN};
+        case Timer_Key::S_TIM16: return {Bus::APB2, &RCC->APB2ENR, RCC_APB2ENR_TIM16EN};
+        case Timer_Key::S_TIM17: return {Bus::APB2, &RCC->APB2ENR, RCC_APB2ENR_TIM17EN};
+        case Timer_Key::NUM_TIMERS:
+        case Timer_Key::S_TIM_INVALID:
+            assert(false);
+            return {Bus::INVALID, nullptr, 0};; //Unreachable
+    }
+
+    __builtin_unreachable();
+}
+
+//Get actual register value based on enum
+constexpr volatile TIM_TypeDef* getTimerRegister(Timer_Key t) {
+    switch(t) {
+        case Timer_Key::S_TIM1:  return TIM1;
+        case Timer_Key::S_TIM2:  return TIM2;
+        case Timer_Key::S_TIM3:  return TIM3;
+        case Timer_Key::S_TIM14:  return TIM14;
+        case Timer_Key::S_TIM15:  return TIM15;
+        case Timer_Key::S_TIM16:  return TIM16;
+        case Timer_Key::S_TIM17:  return TIM17;
+        case Timer_Key::NUM_TIMERS:
+        case Timer_Key::S_TIM_INVALID:
+            assert(false);
+            return nullptr; //Unreachable
+    }
+    __builtin_unreachable();
+}
+
+constexpr IRQn_Type getIRQn(Timer_Key t) {
+    switch(t) {
+        case Timer_Key::S_TIM1:  return TIM1_BRK_UP_TRG_COM_IRQn;
+        case Timer_Key::S_TIM2:  return TIM2_IRQn;
+        case Timer_Key::S_TIM3:  return TIM3_IRQn;
+        case Timer_Key::S_TIM14: return TIM14_IRQn;
+        case Timer_Key::S_TIM15: return TIM15_IRQn;
+        case Timer_Key::S_TIM16: return TIM16_IRQn;
+        case Timer_Key::S_TIM17: return TIM17_IRQn;
+        case Timer_Key::NUM_TIMERS:
+        case Timer_Key::S_TIM_INVALID:
+            assert(false);
+            return TIM1_BRK_UP_TRG_COM_IRQn; //Unreachable
+    }
+    __builtin_unreachable();
+}
+
+
+
+#endif

Core/Include/Timer/SHAL_TIM.h

@@ -0,0 +1,56 @@
+#ifndef SHAL_TIM_H
+#define SHAL_TIM_H
+
+#include "SHAL_TIM_REG.h"
+#include "SHAL_TIM_CALLBACK.h"
+
+#include <array>
+
+class Timer {
+    friend class TimerManager;
+public:
+
+    //Starts the counter
+    void start();
+
+    //Stops the counter
+    void stop();
+
+    //Set prescaler value
+    void setPrescaler(uint16_t presc);
+
+    //Set auto reload register
+    void setARR(uint16_t arr);
+
+    //Enable interrupts
+    void enableInterrupt();
+
+    //Set timer IRQ callback function
+    void setCallbackFunc(TimerCallback callback){
+        registerTimerCallback(timer, callback);
+    }
+
+private:
+
+    explicit Timer(Timer_Key t);
+    Timer();
+
+    Timer_Key timer;
+    volatile TIM_TypeDef* timer_reg;
+
+};
+
+#define getTimer(timer_key) TimerManager::get(timer_key);
+
+//Manages all timers so user does not have to personally initialize
+class TimerManager{
+public:
+
+    static Timer& get(Timer_Key);
+    TimerManager() = delete;
+
+private:
+    inline static Timer timers[static_cast<int>(Timer_Key::NUM_TIMERS)] = {};
+};
+
+#endif

Core/Src/Reg/SHAL_TIM.cpp

@@ -0,0 +1,54 @@
+//
+// Created by Luca on 8/28/2025.
+//
+
+#include "Core/Include/Timer/SHAL_TIM.h"
+#include <cassert>
+
+Timer::Timer(Timer_Key t) : timer(t), timer_reg(getTimerRegister(t)){
+    RCC_Peripheral rcc = getTimerRCC(timer);
+    *rcc.reg |= rcc.bitmask;
+}
+
+Timer::Timer() : timer(Timer_Key::S_TIM_INVALID), timer_reg(nullptr){
+
+}
+
+void Timer::start() {
+    timer_reg->CR1 |= TIM_CR1_CEN;
+    timer_reg->EGR |= TIM_EGR_UG; //load prescaler reg and ARR
+    enableInterrupt();
+}
+
+void Timer::stop() {
+    timer_reg->CR1 &= ~TIM_CR1_CEN;
+}
+
+void Timer::setPrescaler(uint16_t presc) {
+    timer_reg->PSC = presc;
+}
+
+void Timer::setARR(uint16_t arr) {
+    timer_reg->ARR = arr;
+}
+
+void Timer::enableInterrupt() {
+    timer_reg->DIER |= TIM_DIER_UIE;
+    NVIC_EnableIRQ(getIRQn(timer));
+}
+
+
+Timer &TimerManager::get(Timer_Key timer_key) {
+
+    //Ensure that we don't try to get invalid timers
+    assert(timer_key != Timer_Key::S_TIM_INVALID && timer_key != Timer_Key::NUM_TIMERS);
+
+    Timer& selected = timers[static_cast<int>(timer_key)];
+
+    //Timer queried is not initialized yet (defaults to invalid)
+    if(selected.timer == Timer_Key::S_TIM_INVALID){
+        timers[static_cast<int>(timer_key)] = Timer(timer_key); //Initialize timer
+    }
+
+    return timers[static_cast<int>(timer_key)];
+}

Core/Src/Reg/SHAL_TIM_CALLBACK.cpp

@@ -0,0 +1,17 @@
+//
+// Created by Luca on 8/28/2025.
+//
+
+#include "SHAL_TIM_CALLBACK.h"
+
+DEFINE_TIMER_IRQ(Timer_Key::S_TIM1, TIM1_BRK_UP_TRG_COM_IRQHandler)
+DEFINE_TIMER_IRQ(Timer_Key::S_TIM2, TIM2_IRQHandler)
+DEFINE_TIMER_IRQ(Timer_Key::S_TIM3, TIM3_IRQHandler)
+DEFINE_TIMER_IRQ(Timer_Key::S_TIM14, TIM14_IRQHandler)
+DEFINE_TIMER_IRQ(Timer_Key::S_TIM15, TIM15_IRQHandler)
+DEFINE_TIMER_IRQ(Timer_Key::S_TIM16, TIM16_IRQHandler)
+DEFINE_TIMER_IRQ(Timer_Key::S_TIM17, TIM17_IRQHandler)
+
+void registerTimerCallback(Timer_Key key, TimerCallback callback){
+    timer_callbacks[static_cast<int>(key)] = callback;
+}

Core/Src/main.cpp

@@ -1,16 +1,6 @@
 #include "SHAL.h"
 #include "stm32f0xx.h"
 
-volatile int prev_button = false;
-volatile int curr_button = false;
-
-extern "C" void TIM2_IRQHandler(void){
-	if(TIM2->SR & TIM_SR_UIF){
-		TIM2->SR &= ~TIM_SR_UIF;
-		GPIOA->ODR ^= (1 << 4);
-	}
-}
-
 extern "C" void EXTI0_1_IRQHandler(void) {
     if (EXTI->PR & (1 << 0)) {   //Check pending flag
         EXTI->PR |= (1 << 0);    //Clear it by writing 1
@@ -18,13 +8,23 @@ extern "C" void EXTI0_1_IRQHandler(void) {
     }
 }
 
+void tim2Handler(){
+    GPIOA->ODR ^= (1 << 4);
+}
+
 int main() {
     RCC->AHBENR |= RCC_AHBENR_GPIOAEN;
     RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
-    RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
-    RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; // Enable SYSCFG clock (needed for EXTI)
 
-    TIM2->EGR |= TIM_EGR_UG;   //Force update to load PSC/ARR
+    Timer timer2 = getTimer(Timer_Key::S_TIM2);
+
+    timer2.setPrescaler(8000 - 1);
+    timer2.setARR(500 - 1);
+    timer2.setCallbackFunc(tim2Handler);
+    timer2.start();
+
+
+    RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; //Enable SYSCFG clock (needed for EXTI)
 
     GPIOA->MODER &= ~(0b11 << (4 * 2));
     GPIOA->MODER |= (0b1 << (4 * 2));
@@ -35,21 +35,12 @@ int main() {
     GPIOB->MODER &= ~(0x3 << (0 * 2));
     GPIOB->MODER |=  (0x0 << (0 * 2));
 
-    TIM2->PSC = 8000 - 1; //8MHz base, prescaler
-    TIM2->ARR = 500 - 1; //500ms, auto reload register
-
     SYSCFG->EXTICR[0] &= ~SYSCFG_EXTICR1_EXTI0; // Clear EXTI0 mapping
     SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI0_PB; // Map PA0 -> EXTI0
 
     EXTI->IMR |= (1 << 0);   // Unmask EXTI0
     EXTI->RTSR |= (1 << 0);  // Trigger on rising edge
 
-
-    TIM2->DIER |= TIM_DIER_UIE; //Interrupt register
-    TIM2->CR1 |= TIM_CR1_CEN; //Counter enable
-
-
-    NVIC_EnableIRQ(TIM2_IRQn);
     NVIC_EnableIRQ(EXTI0_1_IRQn); // EXTI lines 0 and 1 share an IRQ vector
 
     __enable_irq();