Start timer abstractions

Core/Include/Reg/SHAL_TIM_REG.h

@@ -1,12 +1,69 @@
-#ifndef SHAL_TIM_REG
-#define SHAL_TIM_REG
+#ifndef SHAL_TIM_REG_H
+#define SHAL_TIM_REG_H
 
+#include <cstdint>
+#include <stm32f072xb.h>
 
-#include "stm32f0xx.h"  // Or your device header
-
-enum class S_TIM{ //Sample
-    S_TIM_1 = 0xFFA0,
-    S_TIM_2 = 0xFF,
+enum class Bus {
+    AHB,
+    APB1,
+    APB2
 };
 
+struct RCC_Peripheral {
+    Bus bus;
+    volatile uint32_t* reg;
+    uint32_t bitmask;
+};
+
+enum class Timer_Key { //For STM32F072
+    S_TIM1,
+    S_TIM2,
+    S_TIM3,
+    S_TIM14,
+    S_TIM15,
+    S_TIM16,
+    S_TIM17
+};
+
+//Get timer peripheral struct including bus register, enable mask, timer mask
+constexpr RCC_Peripheral getTimerRCC(Timer_Key t) {
+    switch(t) {
+        case Timer_Key::S_TIM1:  return {Bus::APB2, &RCC->APB2ENR, RCC_APB2ENR_TIM1EN};
+        case Timer_Key::S_TIM2:  return {Bus::APB1, &RCC->APB1ENR, RCC_APB1ENR_TIM2EN};
+        case Timer_Key::S_TIM3:  return {Bus::APB1, &RCC->APB1ENR, RCC_APB1ENR_TIM3EN};
+        case Timer_Key::S_TIM14: return {Bus::APB1, &RCC->APB1ENR, RCC_APB1ENR_TIM14EN};
+        case Timer_Key::S_TIM15: return {Bus::APB2, &RCC->APB2ENR, RCC_APB2ENR_TIM15EN};
+        case Timer_Key::S_TIM16: return {Bus::APB2, &RCC->APB2ENR, RCC_APB2ENR_TIM16EN};
+        case Timer_Key::S_TIM17: return {Bus::APB2, &RCC->APB2ENR, RCC_APB2ENR_TIM17EN};
+    }
+}
+
+//Get actual register value based on enum
+constexpr volatile TIM_TypeDef* getTimerRegister(Timer_Key t) {
+    switch(t) {
+        case Timer_Key::S_TIM1:  return TIM1;
+        case Timer_Key::S_TIM2:  return TIM2;
+        case Timer_Key::S_TIM3:  return TIM3;
+        case Timer_Key::S_TIM14:  return TIM14;
+        case Timer_Key::S_TIM15:  return TIM15;
+        case Timer_Key::S_TIM16:  return TIM16;
+        case Timer_Key::S_TIM17:  return TIM17;
+    }
+}
+
+constexpr IRQn_Type getIRQn(Timer_Key t) {
+    switch(t) {
+        case Timer_Key::S_TIM1:  return TIM1_BRK_UP_TRG_COM_IRQn;
+        case Timer_Key::S_TIM2:  return TIM2_IRQn;
+        case Timer_Key::S_TIM3:  return TIM3_IRQn;
+        case Timer_Key::S_TIM14: return TIM14_IRQn;
+        case Timer_Key::S_TIM15: return TIM15_IRQn;
+        case Timer_Key::S_TIM16: return TIM16_IRQn;
+        case Timer_Key::S_TIM17: return TIM17_IRQn;
+    }
+}
+
+
+
 #endif

Core/Include/SHAL_TIM.h

@@ -5,4 +5,35 @@
 
 
 
+class Timer {
+public:
+
+    explicit Timer(Timer_Key t);
+
+    //Starts the counter
+    void start();
+
+    //Stops the counter
+    void stop();
+
+    void setPrescaler(uint16_t presc);
+
+    void setARR(uint16_t arr);
+
+    void enableInterrupt();
+
+private:
+
+    Timer_Key timer;
+    volatile TIM_TypeDef* timer_reg;
+
+};
+
+extern "C" void TIM2_IRQHandler(void){
+    if(TIM2->SR & TIM_SR_UIF) {
+
+    }
+}
+
+
 #endif

Core/Src/Reg/SHAL_TIM.cpp

@@ -0,0 +1,33 @@
+//
+// Created by Luca on 8/28/2025.
+//
+
+#include "SHAL_TIM.h"
+
+Timer::Timer(Timer_Key t) : timer(t), timer_reg(getTimerRegister(t)){
+    RCC_Peripheral rcc = getTimerRCC(timer);
+    *rcc.reg |= rcc.bitmask;
+}
+
+void Timer::start() {
+    timer_reg->CR1 |= TIM_CR1_CEN;
+}
+
+void Timer::stop() {
+    timer_reg->CR1 &= ~TIM_CR1_CEN;
+}
+
+void Timer::setPrescaler(uint16_t presc) {
+    timer_reg->PSC = presc;
+}
+
+void Timer::setARR(uint16_t arr) {
+    timer_reg->ARR = arr;
+}
+
+void Timer::enableInterrupt() {
+    timer_reg->DIER |= TIM_DIER_UIE;
+    NVIC_EnableIRQ(getIRQn(timer));
+}
+
+

Core/Src/main.cpp

@@ -21,7 +21,9 @@ extern "C" void EXTI0_1_IRQHandler(void) {
 int main() {
     RCC->AHBENR |= RCC_AHBENR_GPIOAEN;
     RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
+
     RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
+
     RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; // Enable SYSCFG clock (needed for EXTI)
 
     TIM2->EGR |= TIM_EGR_UG;   //Force update to load PSC/ARR