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Continuing ADC port

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This commit is contained in:
Ea-r-th
2025-10-15 16:40:27 -07:00
parent cba6c00562
commit 3561879c24
3 changed files with 37 additions and 13 deletions
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24
SHAL/Include/Peripheral/ADC/Reg/SHAL_ADC_REG_L432KC.h
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@@ -70,9 +70,7 @@ SHAL_ADC_Data_Reg getADCDataReg(ADC_Key key){
}
SHAL_ADC_Clock_Reg getADCClockSelectRegister(ADC_Clock_Source clockSource) {
constexpr uint32_t ADCSEL_MASK = RCC_CCIPR_ADCSEL_Msk; // covers bits 29:28
SHAL_ADC_Clock_Reg res = {&RCC->CCIPR, ADCSEL_MASK, 1U << RCC_CCIPR_ADCSEL_Pos}; //Default to PLLSAI1
SHAL_ADC_Clock_Reg res = {&RCC->CCIPR, RCC_CCIPR_ADCSEL_Msk, 1U << RCC_CCIPR_ADCSEL_Pos}; //Default to PLLSAI1
switch(clockSource){
case ADC_Clock_Source::SHAL_PLLSAI1:
@@ -84,10 +82,28 @@ SHAL_ADC_Clock_Reg getADCClockSelectRegister(ADC_Clock_Source clockSource) {
case ADC_Clock_Source::SHAL_MSI:
break; //TODO implement this
}
return res;
}
SHAL_ADC_Channel_Sampling_Time_Reg getADCChannelSamplingTimeRegister(ADC_Key key, SHAL_ADC_Channel channel){
volatile ADC_TypeDef* ADCReg = ADC_TABLE[static_cast<uint8_t>(key)];
volatile uint32_t* SMPReg = nullptr;
uint32_t pos = 0;
auto channelNum = static_cast<uint8_t>(channel);
if (channelNum <= 9) {
SMPReg = &ADCReg->SQR1;
pos = (channelNum * 3);
} else {
SMPReg = &ADCReg->SQR2;
pos = ((channelNum - 10) * 3);
}
return {SMPReg, pos};
}
constexpr ADC_TypeDef* getADCRegister(ADC_Key key){
switch(key){
case ADC_Key::S_ADC1:

21
SHAL/Include/Peripheral/ADC/SHAL_ADC_TYPES.h
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@@ -53,6 +53,11 @@ struct SHAL_ADC_Clock_Reg {
uint32_t mask;
};
struct SHAL_ADC_Channel_Sampling_Time_Reg {
volatile uint32_t* reg;
uint32_t channel_offset;
};
enum class SHAL_ADC_Channel : uint32_t {
CH0,
@@ -77,14 +82,14 @@ enum class SHAL_ADC_Channel : uint32_t {
};
enum class ADC_SampleTime : uint32_t {
C2 = 0x00, //1.5 cycles per sample
C7 = 0x01, //7.5 cycles
C13 = 0x02, //13.5 cycles
C28 = 0x03, //28.5 cycles
C41 = 0x04, //41.5 cycles
C55 = 0x05, //55.5 cycles
C71 = 0x06, //71.5 cycles
C239 = 0x07 //239.5 cycles
C1 = 0x00, //1.5 cycles per sample F0
C2 = 0x01, //7.5 cycles
C3 = 0x02, //13.5 cycles
C4 = 0x03, //28.5 cycles
C5 = 0x04, //41.5 cycles
C6 = 0x05, //55.5 cycles
C7 = 0x06, //71.5 cycles
C8 = 0x07 //239.5 cycles
};
enum class SHAL_ADC_Resolution : uint8_t {

5
SHAL/Src/STM32L4XX/Peripheral/ADC/SHAL_ADC.cpp
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@@ -32,6 +32,9 @@ SHAL_Result SHAL_ADC::init() {
return SHAL_Result::ERROR;
}
configureAlignment(SHAL_ADC_Alignment::RIGHT);
configureResolution(SHAL_ADC_Resolution::B12);
return SHAL_Result::OKAY;
}
@@ -124,7 +127,7 @@ SHAL_Result SHAL_ADC::configureResolution(SHAL_ADC_Resolution resolution) {
SHAL_ADC_Config_Reg config_reg = getADCConfigReg(m_ADCKey);
SHAL_set_bits(config_reg.reg,2)
SHAL_set_bits(config_reg.reg,2,static_cast<uint8_t>(resolution),config_reg.resolution_offset);
return SHAL_Result::OKAY;
}