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Issue: cannot read core

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This commit is contained in:
Ea-r-th
2025-10-17 12:50:16 -07:00
parent 04f79cc543
commit e822b8d9ec
11 changed files with 80 additions and 114 deletions
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20
SHAL/Include/Peripheral/ADC/Reg/SHAL_ADC_REG_L432KC.h
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@@ -54,18 +54,18 @@ static volatile ADC_TypeDef* ADC_TABLE[1] = { //Lookup table for ADCs
ADC1,
};
SHAL_ADC_Common_Control_Reg getADCCommonControl() {
static inline SHAL_ADC_Common_Control_Reg getADCCommonControl() {
return {&ADC1_COMMON->CCR ,ADC_CCR_VREFEN,ADC_CCR_TSEN,ADC_CCR_VBATEN};
}
SHAL_ADC_RCC_Enable_Reg getADCRCCEnableRegister(ADC_Key key){
static inline SHAL_ADC_RCC_Enable_Reg getADCRCCEnableRegister(ADC_Key key){
SHAL_ADC_RCC_Enable_Reg res = {nullptr, RCC_AHB2ENR_ADCEN};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->ISR);
return res;
}
SHAL_ADC_Control_Reg getADCControlReg(ADC_Key key) {
static inline SHAL_ADC_Control_Reg getADCControlReg(ADC_Key key) {
SHAL_ADC_Control_Reg res = {nullptr, ADC_CR_ADEN, ADC_CR_ADDIS, ADC_CR_ADCAL, ADC_CR_ADSTART};
@@ -73,7 +73,7 @@ SHAL_ADC_Control_Reg getADCControlReg(ADC_Key key) {
return res;
}
SHAL_ADC_Config_Reg getADCConfigReg(ADC_Key key) {
static inline SHAL_ADC_Config_Reg getADCConfigReg(ADC_Key key) {
SHAL_ADC_Config_Reg res = {nullptr, ADC_CFGR_CONT, ADC_CFGR_RES_Pos, ADC_CFGR_ALIGN_Pos};
@@ -81,21 +81,21 @@ SHAL_ADC_Config_Reg getADCConfigReg(ADC_Key key) {
return res;
}
SHAL_ADC_ISR_Reg getADCISRReg(ADC_Key key){
static inline SHAL_ADC_ISR_Reg getADCISRReg(ADC_Key key){
SHAL_ADC_ISR_Reg res = {nullptr, ADC_ISR_EOC, ADC_ISR_EOS, ADC_ISR_ADRDY};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->ISR);
return res;
}
SHAL_ADC_Data_Reg getADCDataReg(ADC_Key key){
static inline SHAL_ADC_Data_Reg getADCDataReg(ADC_Key key){
SHAL_ADC_Data_Reg res = {nullptr, 0xFFFF};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->DR);
return res;
}
SHAL_ADC_Clock_Reg getADCClockSelectRegister(ADC_Clock_Source clockSource) {
static inline SHAL_ADC_Clock_Reg getADCClockSelectRegister(ADC_Clock_Source clockSource) {
SHAL_ADC_Clock_Reg res = {&RCC->CCIPR, RCC_CCIPR_ADCSEL_Msk, 1U << RCC_CCIPR_ADCSEL_Pos}; //Default to PLLSAI1
switch(clockSource){
@@ -111,7 +111,7 @@ SHAL_ADC_Clock_Reg getADCClockSelectRegister(ADC_Clock_Source clockSource) {
return res;
}
SHAL_ADC_Channel_Sampling_Time_Reg getADCChannelSamplingTimeRegister(ADC_Key key, SHAL_ADC_Channel channel){
static inline SHAL_ADC_Channel_Sampling_Time_Reg getADCChannelSamplingTimeRegister(ADC_Key key, SHAL_ADC_Channel channel){
volatile ADC_TypeDef* ADCReg = ADC_TABLE[static_cast<uint8_t>(key)];
volatile uint32_t* SMPReg = nullptr;
@@ -130,14 +130,14 @@ SHAL_ADC_Channel_Sampling_Time_Reg getADCChannelSamplingTimeRegister(ADC_Key key
return {SMPReg, pos};
}
SHAL_ADC_Sequence_Amount_Reg getADCSequenceAmountRegister(ADC_Key key){
static inline SHAL_ADC_Sequence_Amount_Reg getADCSequenceAmountRegister(ADC_Key key){
SHAL_ADC_Sequence_Amount_Reg res = {nullptr, ADC_SQR1_L_Pos};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->SQR1);
return res;
}
SHAL_ADC_Sequence_Reg getADCSequenceRegisters(ADC_Key key){
static inline SHAL_ADC_Sequence_Reg getADCSequenceRegisters(ADC_Key key){
volatile ADC_TypeDef* adc_reg = ADC_TABLE[static_cast<uint8_t>(key)];

16
SHAL/Include/Peripheral/EXT/Reg/SHAL_EXTI_REG_L432KC.h
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@@ -6,7 +6,23 @@
#define SHMINGO_HAL_SHAL_EXTI_REG_L432KC_H
#include "SHAL_CORE.h"
#include "SHAL_EXTI_TYPES.h"
#define EXTI_PENDING_REG(line) ((line) < 32 ? EXTI->PR1 : EXTI->PR2)
static inline SHAL_EXTI_Interrupt_Mask_Register getEXTIInterruptMaskRegister(uint32_t line){
auto imr = line < 32 ? EXTI->IMR1 : EXTI->IMR2;
return {&imr};
}
static inline SHAL_EXTI_Rising_Trigger_Selection_Register getEXTIRisingTriggerSelectionRegister(uint32_t line){
auto reg = line < 32 ? EXTI->RTSR1 : EXTI->RTSR2;
return {&reg};
}
static inline SHAL_EXTI_Falling_Trigger_Selection_Register getEXTIFallingTriggerSelectionRegister(uint32_t line){
auto reg = line < 32 ? EXTI->FTSR1 : EXTI->FTSR2;
return {&reg};
}
#endif //SHMINGO_HAL_SHAL_EXTI_REG_L432KC_H

22
SHAL/Include/Peripheral/EXT/SHAL_EXTI_TYPES.h Normal file
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@@ -0,0 +1,22 @@
//
// Created by Luca on 10/17/2025.
//
#ifndef SHMINGO_HAL_SHAL_EXTI_TYPES_H
#define SHMINGO_HAL_SHAL_EXTI_TYPES_H
#include "SHAL_CORE.h"
struct SHAL_EXTI_Interrupt_Mask_Register {
volatile uint32_t* reg;
};
struct SHAL_EXTI_Rising_Trigger_Selection_Register {
volatile uint32_t* reg;
};
struct SHAL_EXTI_Falling_Trigger_Selection_Register {
volatile uint32_t* reg;
};
#endif //SHMINGO_HAL_SHAL_EXTI_TYPES_H

2
SHAL/Include/Peripheral/I2C/Reg/SHAL_I2C_REG_L432KC.h
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@@ -8,6 +8,8 @@
#include "SHAL_CORE.h"
#include "SHAL_I2C_TYPES.h"
#define NUM_I2C_BUSES 3
enum class I2C_Pair : uint8_t{
//I2C_1
SCL1A9_SDA1A10, //AF4

5
SHAL/Include/Peripheral/Timer/SHAL_TIM_CALLBACK.h
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@@ -13,11 +13,12 @@
#include "SHAL_CORE.h"
#include "SHAL_TIM_REG.h"
#define DEFINE_TIMER_IRQ(key, irq_handler) \
extern "C" void irq_handler(void) { \
auto tim_status_reg = getTimerStatusRegister(key) \
auto tim_status_reg = getTimerStatusRegister(key); \
if (*tim_status_reg.reg & tim_status_reg.update_interrupt_flag_mask) { \
SHAL_clear_mask(tim_status_reg.reg,tim_status_reg.update_interrupt_flag_mask) /* clear flag */ \
SHAL_clear_bitmask(tim_status_reg.reg,tim_status_reg.update_interrupt_flag_mask); /* clear flag */ \
auto cb = timer_callbacks[static_cast<int>(key)]; \
if (cb) cb(); \
}; \