Made timer constructor unaccessable by user

This commit is contained in:
2025-08-28 22:02:08 -07:00
parent 1e966f0688
commit d092ccd362
4 changed files with 60 additions and 12 deletions

View File

@@ -2,8 +2,10 @@
#define SHAL_TIM_REG_H #define SHAL_TIM_REG_H
#include <cstdint> #include <cstdint>
#include <cassert>
#include <stm32f072xb.h> #include <stm32f072xb.h>
enum class Bus { enum class Bus {
AHB, AHB,
APB1, APB1,
@@ -25,7 +27,8 @@ enum class Timer_Key { //For STM32F072
S_TIM15, S_TIM15,
S_TIM16, S_TIM16,
S_TIM17, S_TIM17,
NUM_TIMERS NUM_TIMERS,
S_TIM_INVALID
}; };
@@ -39,10 +42,13 @@ constexpr RCC_Peripheral getTimerRCC(Timer_Key t) {
case Timer_Key::S_TIM15: return {Bus::APB2, &RCC->APB2ENR, RCC_APB2ENR_TIM15EN}; case Timer_Key::S_TIM15: return {Bus::APB2, &RCC->APB2ENR, RCC_APB2ENR_TIM15EN};
case Timer_Key::S_TIM16: return {Bus::APB2, &RCC->APB2ENR, RCC_APB2ENR_TIM16EN}; case Timer_Key::S_TIM16: return {Bus::APB2, &RCC->APB2ENR, RCC_APB2ENR_TIM16EN};
case Timer_Key::S_TIM17: return {Bus::APB2, &RCC->APB2ENR, RCC_APB2ENR_TIM17EN}; case Timer_Key::S_TIM17: return {Bus::APB2, &RCC->APB2ENR, RCC_APB2ENR_TIM17EN};
case Timer_Key::NUM_TIMERS: return {Bus::INVALID, nullptr, 0};; case Timer_Key::NUM_TIMERS:
case Timer_Key::S_TIM_INVALID:
assert(false);
return {Bus::INVALID, nullptr, 0};; //Unreachable
} }
return {Bus::APB2, &RCC->APB2ENR, RCC_APB2ENR_TIM1EN}; __builtin_unreachable();
} }
//Get actual register value based on enum //Get actual register value based on enum
@@ -55,9 +61,12 @@ constexpr volatile TIM_TypeDef* getTimerRegister(Timer_Key t) {
case Timer_Key::S_TIM15: return TIM15; case Timer_Key::S_TIM15: return TIM15;
case Timer_Key::S_TIM16: return TIM16; case Timer_Key::S_TIM16: return TIM16;
case Timer_Key::S_TIM17: return TIM17; case Timer_Key::S_TIM17: return TIM17;
case Timer_Key::NUM_TIMERS: return nullptr; case Timer_Key::NUM_TIMERS:
case Timer_Key::S_TIM_INVALID:
assert(false);
return nullptr; //Unreachable
} }
return TIM1; __builtin_unreachable();
} }
constexpr IRQn_Type getIRQn(Timer_Key t) { constexpr IRQn_Type getIRQn(Timer_Key t) {
@@ -69,9 +78,12 @@ constexpr IRQn_Type getIRQn(Timer_Key t) {
case Timer_Key::S_TIM15: return TIM15_IRQn; case Timer_Key::S_TIM15: return TIM15_IRQn;
case Timer_Key::S_TIM16: return TIM16_IRQn; case Timer_Key::S_TIM16: return TIM16_IRQn;
case Timer_Key::S_TIM17: return TIM17_IRQn; case Timer_Key::S_TIM17: return TIM17_IRQn;
case Timer_Key::NUM_TIMERS: return TIM1_BRK_UP_TRG_COM_IRQn; case Timer_Key::NUM_TIMERS:
case Timer_Key::S_TIM_INVALID:
assert(false);
return TIM1_BRK_UP_TRG_COM_IRQn; //Unreachable
} }
return TIM1_BRK_UP_TRG_COM_IRQn; __builtin_unreachable();
} }

View File

@@ -4,10 +4,11 @@
#include "SHAL_TIM_REG.h" #include "SHAL_TIM_REG.h"
#include "SHAL_TIM_CALLBACK.h" #include "SHAL_TIM_CALLBACK.h"
class Timer { #include <array>
public:
explicit Timer(Timer_Key t); class Timer {
friend class TimerManager;
public:
//Starts the counter //Starts the counter
void start(); void start();
@@ -31,9 +32,25 @@ public:
private: private:
explicit Timer(Timer_Key t);
Timer();
Timer_Key timer; Timer_Key timer;
volatile TIM_TypeDef* timer_reg; volatile TIM_TypeDef* timer_reg;
}; };
#define getTimer(timer_key) TimerManager::get(timer_key);
//Manages all timers so user does not have to personally initialize
class TimerManager{
public:
static Timer& get(Timer_Key);
TimerManager() = delete;
private:
inline static Timer timers[static_cast<int>(Timer_Key::NUM_TIMERS)] = {};
};
#endif #endif

View File

@@ -3,12 +3,17 @@
// //
#include "SHAL_TIM.h" #include "SHAL_TIM.h"
#include <cassert>
Timer::Timer(Timer_Key t) : timer(t), timer_reg(getTimerRegister(t)){ Timer::Timer(Timer_Key t) : timer(t), timer_reg(getTimerRegister(t)){
RCC_Peripheral rcc = getTimerRCC(timer); RCC_Peripheral rcc = getTimerRCC(timer);
*rcc.reg |= rcc.bitmask; *rcc.reg |= rcc.bitmask;
} }
Timer::Timer() : timer(Timer_Key::S_TIM_INVALID), timer_reg(nullptr){
}
void Timer::start() { void Timer::start() {
timer_reg->CR1 |= TIM_CR1_CEN; timer_reg->CR1 |= TIM_CR1_CEN;
timer_reg->EGR |= TIM_EGR_UG; //load prescaler reg and ARR timer_reg->EGR |= TIM_EGR_UG; //load prescaler reg and ARR
@@ -33,3 +38,17 @@ void Timer::enableInterrupt() {
} }
Timer &TimerManager::get(Timer_Key timer_key) {
//Ensure that we don't try to get invalid timers
assert(timer_key != Timer_Key::S_TIM_INVALID && timer_key != Timer_Key::NUM_TIMERS);
Timer& selected = timers[static_cast<int>(timer_key)];
//Timer queried is not initialized yet (defaults to invalid)
if(selected.timer == Timer_Key::S_TIM_INVALID){
timers[static_cast<int>(timer_key)] = Timer(timer_key); //Initialize timer
}
return timers[static_cast<int>(timer_key)];
}

View File

@@ -16,10 +16,10 @@ int main() {
RCC->AHBENR |= RCC_AHBENR_GPIOAEN; RCC->AHBENR |= RCC_AHBENR_GPIOAEN;
RCC->AHBENR |= RCC_AHBENR_GPIOBEN; RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
auto timer2 = Timer(Timer_Key::S_TIM2); Timer timer2 = getTimer(Timer_Key::S_TIM2);
timer2.setPrescaler(8000 - 1); timer2.setPrescaler(8000 - 1);
timer2.setARR(250 - 1); timer2.setARR(500 - 1);
timer2.setCallbackFunc(tim2Handler); timer2.setCallbackFunc(tim2Handler);
timer2.start(); timer2.start();