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Finished ADC, updating timer code

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This commit is contained in:
Ea-r-th
2025-10-17 00:59:12 -07:00
parent af21480aff
commit 6c8fa459f8
14 changed files with 267 additions and 164 deletions
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4
SHAL/Include/Peripheral/ADC/Reg/SHAL_ADC_REG_L432KC.h
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@@ -81,8 +81,8 @@ SHAL_ADC_Config_Reg getADCConfigReg(ADC_Key key) {
return res;
}
SHAL_ADC_ISR getADCISR(ADC_Key key){
SHAL_ADC_ISR res = {nullptr, ADC_ISR_EOC};
SHAL_ADC_ISR_Reg getADCISRReg(ADC_Key key){
SHAL_ADC_ISR_Reg res = {nullptr, ADC_ISR_EOC, ADC_ISR_EOS, ADC_ISR_ADRDY};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->ISR);
return res;

7
SHAL/Include/Peripheral/ADC/SHAL_ADC.h
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@@ -35,7 +35,7 @@ public:
/// \param numChannels Number of channels to convert
/// \param result Pointer to store converted channel results in
/// \param time SHAL_ADC_SampleTime - amount of clock cycles per conversion
void multiConvertSingle(SHAL_ADC_Channel* channels, int numChannels, uint16_t* result, SHAL_ADC_SampleTime time = SHAL_ADC_SampleTime::C8);
SHAL_Result multiConvertSingle(SHAL_ADC_Channel* channels, int numChannels, uint16_t* result, SHAL_ADC_SampleTime time = SHAL_ADC_SampleTime::C8);
@@ -48,9 +48,14 @@ private:
//Checks to see if instance is initialized with a proper ADC peripheral tag
bool isValid();
//Enabled peripheral
SHAL_Result enable();
//Disables peripheral
SHAL_Result disable();
SHAL_Result startConversion();
/// Adds an ADC channel to the conversion sequence
/// \param channel Channel to add
/// \param index Index to add channel to (ADC channel will be the nth channel to convert

4
SHAL/Include/Peripheral/ADC/SHAL_ADC_TYPES.h
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@@ -44,9 +44,11 @@ struct SHAL_ADC_Data_Reg {
};
//Register for the interrupt service routine for ADCs
struct SHAL_ADC_ISR {
struct SHAL_ADC_ISR_Reg {
volatile uint32_t* reg;
uint32_t end_of_conversion_mask;
uint32_t end_of_sequence_mask;
uint32_t ready_mask;
};
//Register controlling the clock source for the ADC

115
SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_REG_L432KC.h
View File

@@ -16,8 +16,7 @@
#define AVAILABLE_GPIO \
X(A0) X(A1) X(A2) X(A3) X(A4) X(A5) X(A6) X(A7) X(A8) X(A9) X(A10) X(A11) X(A12) X(A13) X(A14) X(A15) \
X(B0) X(B1) X(B2) X(B3) X(B4) X(B5) X(B6) X(B7) X(B8) X(B9) X(B10) X(B11) X(B12) X(B13) X(B14) X(B15) \
X(C0) X(C1) X(C2) X(C3) X(C4) X(C5) X(C6) X(C7) X(C8) X(C9) X(C10) X(C11) X(C12) X(C13) X(C14) X(C15)
X(B0) X(B1) X(B3) X(B4) X(B5) X(B6) X(B7)
//Build enum map of available SHAL_GPIO pins
@@ -29,8 +28,6 @@ enum class GPIO_Key : uint8_t {
INVALID
};
constexpr SHAL_GPIO_Peripheral getGPIORegister(const GPIO_Key g){
switch(g) {
case GPIO_Key::A0: return {GPIOA,0};
@@ -51,36 +48,11 @@ constexpr SHAL_GPIO_Peripheral getGPIORegister(const GPIO_Key g){
case GPIO_Key::A15: return {GPIOA,15};
case GPIO_Key::B0: return {GPIOB,0};
case GPIO_Key::B1: return {GPIOB,1};
case GPIO_Key::B2: return {GPIOB,2};
case GPIO_Key::B3: return {GPIOB,3};
case GPIO_Key::B4: return {GPIOB,4};
case GPIO_Key::B5: return {GPIOB,5};
case GPIO_Key::B6: return {GPIOB,6};
case GPIO_Key::B7: return {GPIOB,7};
case GPIO_Key::B8: return {GPIOB,8};
case GPIO_Key::B9: return {GPIOB,9};
case GPIO_Key::B10: return {GPIOB,10};
case GPIO_Key::B11: return {GPIOB,11};
case GPIO_Key::B12: return {GPIOB,12};
case GPIO_Key::B13: return {GPIOB,13};
case GPIO_Key::B14: return {GPIOB,14};
case GPIO_Key::B15: return {GPIOB,15};
case GPIO_Key::C0: return {GPIOC,0};
case GPIO_Key::C1: return {GPIOC,1};
case GPIO_Key::C2: return {GPIOC,2};
case GPIO_Key::C3: return {GPIOC,3};
case GPIO_Key::C4: return {GPIOC,4};
case GPIO_Key::C5: return {GPIOC,5};
case GPIO_Key::C6: return {GPIOC,6};
case GPIO_Key::C7: return {GPIOC,7};
case GPIO_Key::C8: return {GPIOC,8};
case GPIO_Key::C9: return {GPIOC,9};
case GPIO_Key::C10: return {GPIOC,10};
case GPIO_Key::C11: return {GPIOC,11};
case GPIO_Key::C12: return {GPIOC,12};
case GPIO_Key::C13: return {GPIOC,13};
case GPIO_Key::C14: return {GPIOC,14};
case GPIO_Key::C15: return {GPIOC,15};
case GPIO_Key::INVALID:
case GPIO_Key::NUM_GPIO:
assert(false);
@@ -114,8 +86,7 @@ constexpr SHAL_GPIO_EXTI_Register getGPIOEXTICR(const GPIO_Key g){
case GPIO_Key::B5: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI5_PB,EXTI9_5_IRQn};
case GPIO_Key::B6: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI6_PB,EXTI9_5_IRQn};
case GPIO_Key::B7: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI7_PB,EXTI9_5_IRQn};
case GPIO_Key::C14: return {&SYSCFG->EXTICR[3],SYSCFG_EXTICR4_EXTI14_PC,EXTI15_10_IRQn};
case GPIO_Key::C15: return {&SYSCFG->EXTICR[3],SYSCFG_EXTICR4_EXTI15_PC,EXTI15_10_IRQn};
case GPIO_Key::INVALID:
case GPIO_Key::NUM_GPIO:
@@ -146,38 +117,12 @@ constexpr SHAL_Peripheral_Register getGPIORCCEnable(const GPIO_Key g){
return {&RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN_Pos};
case GPIO_Key::B0:
case GPIO_Key::B1:
case GPIO_Key::B2:
case GPIO_Key::B3:
case GPIO_Key::B4:
case GPIO_Key::B5:
case GPIO_Key::B6:
case GPIO_Key::B7:
case GPIO_Key::B8:
case GPIO_Key::B9:
case GPIO_Key::B10:
case GPIO_Key::B11:
case GPIO_Key::B12:
case GPIO_Key::B13:
case GPIO_Key::B14:
case GPIO_Key::B15:
return {&RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN_Pos};
case GPIO_Key::C0:
case GPIO_Key::C1:
case GPIO_Key::C2:
case GPIO_Key::C3:
case GPIO_Key::C4:
case GPIO_Key::C5:
case GPIO_Key::C6:
case GPIO_Key::C7:
case GPIO_Key::C8:
case GPIO_Key::C9:
case GPIO_Key::C10:
case GPIO_Key::C11:
case GPIO_Key::C12:
case GPIO_Key::C13:
case GPIO_Key::C14:
case GPIO_Key::C15:
return {&RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN_Pos};
case GPIO_Key::INVALID:
case GPIO_Key::NUM_GPIO:
assert(false);
@@ -207,38 +152,11 @@ constexpr uint32_t getGPIOPortNumber(const GPIO_Key g){
return 0;
case GPIO_Key::B0:
case GPIO_Key::B1:
case GPIO_Key::B2:
case GPIO_Key::B3:
case GPIO_Key::B4:
case GPIO_Key::B5:
case GPIO_Key::B6:
case GPIO_Key::B7:
case GPIO_Key::B8:
case GPIO_Key::B9:
case GPIO_Key::B10:
case GPIO_Key::B11:
case GPIO_Key::B12:
case GPIO_Key::B13:
case GPIO_Key::B14:
case GPIO_Key::B15:
return 1;
case GPIO_Key::C0:
case GPIO_Key::C1:
case GPIO_Key::C2:
case GPIO_Key::C3:
case GPIO_Key::C4:
case GPIO_Key::C5:
case GPIO_Key::C6:
case GPIO_Key::C7:
case GPIO_Key::C8:
case GPIO_Key::C9:
case GPIO_Key::C10:
case GPIO_Key::C11:
case GPIO_Key::C12:
case GPIO_Key::C13:
case GPIO_Key::C14:
case GPIO_Key::C15:
return 2;
case GPIO_Key::INVALID:
case GPIO_Key::NUM_GPIO:
assert(false);
@@ -251,67 +169,42 @@ constexpr SHAL_GPIO_Port_Info getGPIOPortInfo(GPIO_Key key){
switch(key){
case GPIO_Key::A0:
case GPIO_Key::B0:
case GPIO_Key::C0:
return {0, SHAL_ADC_Channel::CH0};
case GPIO_Key::A1:
case GPIO_Key::B1:
case GPIO_Key::C1:
return {1, SHAL_ADC_Channel::CH1};
case GPIO_Key::A2:
case GPIO_Key::B2:
case GPIO_Key::C2:
return {2, SHAL_ADC_Channel::CH2};
case GPIO_Key::A3:
case GPIO_Key::B3:
case GPIO_Key::C3:
return {3, SHAL_ADC_Channel::CH3};
case GPIO_Key::A4:
case GPIO_Key::B4:
case GPIO_Key::C4:
return {4, SHAL_ADC_Channel::CH4};
case GPIO_Key::A5:
case GPIO_Key::B5:
case GPIO_Key::C5:
return {5, SHAL_ADC_Channel::CH5};
case GPIO_Key::A6:
case GPIO_Key::B6:
case GPIO_Key::C6:
return {6, SHAL_ADC_Channel::CH6};
case GPIO_Key::A7:
case GPIO_Key::B7:
case GPIO_Key::C7:
return {7, SHAL_ADC_Channel::CH7};
case GPIO_Key::A8:
case GPIO_Key::B8:
case GPIO_Key::C8:
return {8, SHAL_ADC_Channel::CH8};
case GPIO_Key::A9:
case GPIO_Key::B9:
case GPIO_Key::C9:
return {9, SHAL_ADC_Channel::CH9};
case GPIO_Key::A10:
case GPIO_Key::B10:
case GPIO_Key::C10:
return {10, SHAL_ADC_Channel::CH10};
case GPIO_Key::A11:
case GPIO_Key::B11:
case GPIO_Key::C11:
return {11, SHAL_ADC_Channel::CH11};
case GPIO_Key::A12:
case GPIO_Key::B12:
case GPIO_Key::C12:
return {12, SHAL_ADC_Channel::CH12};
case GPIO_Key::A13:
case GPIO_Key::B13:
case GPIO_Key::C13:
return {13, SHAL_ADC_Channel::CH13};
case GPIO_Key::A14:
case GPIO_Key::B14:
case GPIO_Key::C14:
return {14, SHAL_ADC_Channel::CH14};
case GPIO_Key::A15:
case GPIO_Key::B15:
case GPIO_Key::C15:
return {15, SHAL_ADC_Channel::CH15};
case GPIO_Key::NUM_GPIO:
case GPIO_Key::INVALID:
@@ -320,6 +213,4 @@ constexpr SHAL_GPIO_Port_Info getGPIOPortInfo(GPIO_Key key){
__builtin_unreachable();
}
#endif //SHAL_GPIO_REG_F072XB_H
#endif //SHAL_GPIO_REG_F072XB_H

2
SHAL/Include/Peripheral/GPIO/SHAL_GPIO.h
View File

@@ -27,7 +27,7 @@ public:
/// Uses the ADC to read an analog voltage value
/// \param sampleTime The amount of clock cycles to use for the ADC
/// \return ADC result
uint16_t analogRead(SHAL_ADC_SampleTime sampleTime = SHAL_ADC_SampleTime::C239);
uint16_t analogRead(SHAL_ADC_SampleTime sampleTime = SHAL_ADC_SampleTime::C8);
void setPinMode(PinMode mode) volatile;

4
SHAL/Include/Peripheral/Timer/Reg/SHAL_TIM_REG_F072xB.h
View File

@@ -6,8 +6,8 @@
******************************************************************************
*/
#ifndef SHAL_TIM_REG_H
#define SHAL_TIM_REG_H
#ifndef SHAL_TIM_REG_F072XB_H
#define SHAL_TIM_REG_F072XB_H
#include <cassert>
#include <stm32f072xb.h>

122
SHAL/Include/Peripheral/Timer/Reg/SHAL_TIM_REG_L432KC.h Normal file
View File

@@ -0,0 +1,122 @@
/**
******************************************************************************
* @file SHAL_TIM_REG.h
* @author Luca Lizaranzu
* @brief Defines universal macros and objects used across all STM32 families
******************************************************************************
*/
#ifndef SHAL_TIM_REG_L432KC_H
#define SHAL_TIM_REG_L432KC_H
#include <cassert>
#include <stm32l432xx.h>
#include "SHAL_CORE.h"
#include "SHAL_TIM_TYPES.h"
enum class Timer_Key : uint8_t { //For STM32L432
S_TIM1,
S_TIM2,
S_TIM6,
S_TIM7,
S_TIM15,
S_TIM16,
NUM_TIMERS,
S_TIM_INVALID
};
//Lookup table for timer typedefs
static volatile TIM_TypeDef* TIM_TABLE[6] = {
TIM1,
TIM2,
TIM6,
TIM7,
TIM15,
TIM16,
};
#define SHAL_TIM1 TimerManager::get(Timer_Key::S_TIM1)
#define SHAL_TIM2 TimerManager::get(Timer_Key::S_TIM2)
#define SHAL_TIM6 TimerManager::get(Timer_Key::S_TIM6)
#define SHAL_TIM7 TimerManager::get(Timer_Key::S_TIM7)
#define SHAL_TIM15 TimerManager::get(Timer_Key::S_TIM15)
#define SHAL_TIM16 TimerManager::get(Timer_Key::S_TIM16)
static inline SHAL_TIM_Status_Register getTimerStatusRegister(Timer_Key key){
SHAL_TIM_Status_Register res = {nullptr, TIM_SR_UIF};
volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
res.reg = &tim->SR;
return res;
}
static inline SHAL_TIM_Control_Register_1 getTimerControlRegister1(Timer_Key key){
SHAL_TIM_Control_Register_1 res = {nullptr, TIM_CR1_CEN_Msk, TIM_CR1_UDIS, TIM_CR1_OPM, TIM_CR1_CMS_Pos};
volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
res.reg = &tim->CR1;
return res;
}
static inline SHAL_TIM_DMA_Interrupt_Enable_Register getTimerDMAInterruptEnableRegister(Timer_Key key){
SHAL_TIM_DMA_Interrupt_Enable_Register res = {nullptr, TIM_DIER_UIE};
volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
res.reg = &tim->CR1;
return res;
}
static inline SHAL_TIM_Event_Generation_Register getTimerEventGenerationRegister(Timer_Key key){
SHAL_TIM_Event_Generation_Register res = {nullptr, TIM_EGR_UG};
volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
res.reg = &tim->CR1;
return res;
}
//Get TIMER_KEY peripheral struct including bus register, enable mask, TIMER_KEY mask
static inline SHAL_TIM_RCC_Register getTimerRCC(Timer_Key t) {
switch(t) {
case Timer_Key::S_TIM1: return {&RCC->APB2ENR, RCC_APB2ENR_TIM1EN_Pos};
case Timer_Key::S_TIM2: return {&RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN_Pos};
case Timer_Key::S_TIM6: return {&RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN_Pos};
case Timer_Key::S_TIM7: return {&RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN_Pos};
case Timer_Key::S_TIM15: return {&RCC->APB2ENR, RCC_APB2ENR_TIM15EN_Pos};
case Timer_Key::S_TIM16: return {&RCC->APB2ENR, RCC_APB2ENR_TIM16EN_Pos};
case Timer_Key::NUM_TIMERS:
case Timer_Key::S_TIM_INVALID:
assert(false);
}
__builtin_unreachable();
}
static inline IRQn_Type getTimerIRQn(Timer_Key t) {
switch(t) {
case Timer_Key::S_TIM1: return TIM1_TRG_COM_IRQn;
case Timer_Key::S_TIM2: return TIM2_IRQn;
case Timer_Key::S_TIM6: return TIM6_DAC_IRQn;
case Timer_Key::S_TIM7: return TIM7_IRQn;
case Timer_Key::S_TIM15: return TIM1_BRK_TIM15_IRQn;
case Timer_Key::S_TIM16: return TIM1_UP_TIM16_IRQn;
case Timer_Key::NUM_TIMERS:
case Timer_Key::S_TIM_INVALID:
__builtin_unreachable();
}
__builtin_unreachable();
}
#endif

8
SHAL/Include/Peripheral/Timer/SHAL_TIM.h
View File

@@ -9,7 +9,7 @@
#ifndef SHAL_TIM_H
#define SHAL_TIM_H
#include "SHAL_TIM_REG_F072xB.h"
#include "SHAL_TIM_REG.h"
#include "SHAL_TIM_CALLBACK.h"
#include <array>
@@ -18,7 +18,7 @@ class Timer {
friend class TimerManager;
public:
///
/// Initializes a timer
/// \param prescaler The amount of times the base clock has to cycle before the timer adds one to the count
/// \param autoReload The number of timer counts before the count is reset and IRQ is called
void init(uint32_t prescaler, uint32_t autoReload);
@@ -40,7 +40,7 @@ public:
//Set TIMER_KEY IRQ callback function
void setCallbackFunc(TimerCallback callback){
registerTimerCallback(TIMER_KEY, callback);
registerTimerCallback(m_key, callback);
}
private:
@@ -48,7 +48,7 @@ private:
explicit Timer(Timer_Key t);
Timer();
Timer_Key TIMER_KEY;
Timer_Key m_key;
};

8
SHAL/Include/Peripheral/Timer/SHAL_TIM_REG.h
View File

@@ -2,8 +2,8 @@
// Created by Luca on 9/7/2025.
//
#ifndef SHMINGO_HAL_SHAL_TIM_REG_H
#define SHMINGO_HAL_SHAL_TIM_REG_H
#ifndef SHAL_TIM_REG_H
#define SHAL_TIM_REG_H
#if defined(STM32F030x6)
#include "stm32f030x6.h"
@@ -46,7 +46,7 @@
#elif defined(STM32L431xx)
#include "stm32l431xx.h"
#elif defined(STM32L432xx)
#include "stm32l432xx.h"
#include "SHAL_TIM_REG_L432KC.h"
#elif defined(STM32L433xx)
#include "stm32l433xx.h"
#elif defined(STM32L442xx)
@@ -92,4 +92,4 @@
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
#endif
#endif //SHMINGO_HAL_SHAL_TIM_REG_H
#endif //SHAL_TIM_REG_H

31
SHAL/Include/Peripheral/Timer/SHAL_TIM_TYPES.h
View File

@@ -2,14 +2,37 @@
// Created by Luca on 9/7/2025.
//
#ifndef SHMINGO_HAL_SHAL_TIM_TYPES_H
#define SHMINGO_HAL_SHAL_TIM_TYPES_H
#ifndef SHAL_TIM_TYPES_H
#define SHAL_TIM_TYPES_H
#include "SHAL_CORE.h"
struct TIM_RCC_Enable{
volatile uint32_t* busEnableReg;
struct SHAL_TIM_RCC_Register{
volatile uint32_t* reg;
uint32_t offset;
};
struct SHAL_TIM_Control_Register_1 {
volatile uint32_t* reg;
uint32_t counter_enable_mask;
uint32_t update_disable_mask;
uint32_t one_pulse_mode_mask;
uint32_t center_align_mode_offset;
};
struct SHAL_TIM_DMA_Interrupt_Enable_Register {
volatile uint32_t* reg;
uint32_t update_interrupt_enable_mask;
};
struct SHAL_TIM_Status_Register {
volatile uint32_t* reg;
uint32_t update_interrupt_flag_mask;
};
struct SHAL_TIM_Event_Generation_Register {
volatile uint32_t* reg;
uint32_t update_generation_mask;
};
#endif //SHMINGO_HAL_SHAL_TIM_TYPES_H