diff --git a/CMakeLists.txt b/CMakeLists.txt index b2867a8..8326571 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -29,14 +29,17 @@ set(MX_INCLUDE_DIRECTORIES set(PROJECT_INCLUDE_DIRECTORIES ${CMAKE_CURRENT_SOURCE_DIR} - ${CMAKE_CURRENT_SOURCE_DIR}/Core/Include/Timer - ${CMAKE_CURRENT_SOURCE_DIR}/Core/Include/Timer/Reg - ${CMAKE_CURRENT_SOURCE_DIR}/Core/Include + SHAL/Include/Core/ + SHAL/Include/Peripheral/Timer + SHAL/Include/Peripheral/Timer/Reg + SHAL/Include/Peripheral/GPIO + SHAL/Include/Peripheral/GPIO/Reg + ${CMAKE_CURRENT_SOURCE_DIR}/SHAL/Include ) file(GLOB_RECURSE PROJECT_SOURCES - ${CMAKE_CURRENT_SOURCE_DIR}/Core/*.c - ${CMAKE_CURRENT_SOURCE_DIR}/Core/*.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/SHAL/*.c + ${CMAKE_CURRENT_SOURCE_DIR}/SHAL/*.cpp ) add_executable(${EXECUTABLE} diff --git a/Drivers/CMSIS/Include/cmsis_armcc.h b/Drivers/CMSIS/Include/cmsis_armcc.h index 4d9d064..dbf39b7 100644 --- a/Drivers/CMSIS/Include/cmsis_armcc.h +++ b/Drivers/CMSIS/Include/cmsis_armcc.h @@ -101,7 +101,7 @@ #define __RESTRICT __restrict #endif -/* ########################### Core Function Access ########################### */ +/* ########################### SHAL Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ @@ -374,7 +374,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) /*@} end of CMSIS_Core_RegAccFunctions */ -/* ########################## Core Instruction Access ######################### */ +/* ########################## SHAL Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ diff --git a/Drivers/CMSIS/Include/cmsis_armclang.h b/Drivers/CMSIS/Include/cmsis_armclang.h index 162a400..6d6e959 100644 --- a/Drivers/CMSIS/Include/cmsis_armclang.h +++ b/Drivers/CMSIS/Include/cmsis_armclang.h @@ -112,7 +112,7 @@ #endif -/* ########################### Core Function Access ########################### */ +/* ########################### SHAL Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ @@ -770,7 +770,7 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) /*@} end of CMSIS_Core_RegAccFunctions */ -/* ########################## Core Instruction Access ######################### */ +/* ########################## SHAL Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ diff --git a/Drivers/CMSIS/Include/cmsis_gcc.h b/Drivers/CMSIS/Include/cmsis_gcc.h index 2d9db15..83dc08d 100644 --- a/Drivers/CMSIS/Include/cmsis_gcc.h +++ b/Drivers/CMSIS/Include/cmsis_gcc.h @@ -115,7 +115,7 @@ #endif -/* ########################### Core Function Access ########################### */ +/* ########################### SHAL Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ @@ -810,7 +810,7 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) /*@} end of CMSIS_Core_RegAccFunctions */ -/* ########################## Core Instruction Access ######################### */ +/* ########################## SHAL Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ diff --git a/Drivers/CMSIS/Include/core_armv8mbl.h b/Drivers/CMSIS/Include/core_armv8mbl.h index 251e4ed..b558618 100644 --- a/Drivers/CMSIS/Include/core_armv8mbl.h +++ b/Drivers/CMSIS/Include/core_armv8mbl.h @@ -1033,7 +1033,7 @@ typedef struct #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ -/* Debug Core Register Selector Register Definitions */ +/* Debug SHAL Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ @@ -1109,7 +1109,7 @@ typedef struct @{ */ -/* Memory mapping of Core Hardware */ +/* Memory mapping of SHAL Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ @@ -1138,7 +1138,7 @@ typedef struct #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< SHAL Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ @@ -1146,7 +1146,7 @@ typedef struct #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< SHAL Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ diff --git a/Drivers/CMSIS/Include/core_armv8mml.h b/Drivers/CMSIS/Include/core_armv8mml.h index 3a3148e..d4dc687 100644 --- a/Drivers/CMSIS/Include/core_armv8mml.h +++ b/Drivers/CMSIS/Include/core_armv8mml.h @@ -1863,7 +1863,7 @@ typedef struct #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ -/* Debug Core Register Selector Register Definitions */ +/* Debug SHAL Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ @@ -1969,7 +1969,7 @@ typedef struct @{ */ -/* Memory mapping of Core Hardware */ +/* Memory mapping of SHAL Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ @@ -2003,7 +2003,7 @@ typedef struct #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< SHAL Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ @@ -2012,7 +2012,7 @@ typedef struct #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< SHAL Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ diff --git a/Drivers/CMSIS/Include/core_cm0.h b/Drivers/CMSIS/Include/core_cm0.h index f929bba..3e96147 100644 --- a/Drivers/CMSIS/Include/core_cm0.h +++ b/Drivers/CMSIS/Include/core_cm0.h @@ -530,7 +530,7 @@ typedef struct @{ */ -/* Memory mapping of Core Hardware */ +/* Memory mapping of SHAL Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ diff --git a/Drivers/CMSIS/Include/core_cm0plus.h b/Drivers/CMSIS/Include/core_cm0plus.h index 424011a..42937a2 100644 --- a/Drivers/CMSIS/Include/core_cm0plus.h +++ b/Drivers/CMSIS/Include/core_cm0plus.h @@ -644,7 +644,7 @@ typedef struct @{ */ -/* Memory mapping of Core Hardware */ +/* Memory mapping of SHAL Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ diff --git a/Drivers/CMSIS/Include/core_cm1.h b/Drivers/CMSIS/Include/core_cm1.h index 0ed678e..ab501c1 100644 --- a/Drivers/CMSIS/Include/core_cm1.h +++ b/Drivers/CMSIS/Include/core_cm1.h @@ -556,7 +556,7 @@ typedef struct @{ */ -/* Memory mapping of Core Hardware */ +/* Memory mapping of SHAL Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ diff --git a/Drivers/CMSIS/Include/core_cm23.h b/Drivers/CMSIS/Include/core_cm23.h index acbc5df..329f7ae 100644 --- a/Drivers/CMSIS/Include/core_cm23.h +++ b/Drivers/CMSIS/Include/core_cm23.h @@ -1108,7 +1108,7 @@ typedef struct #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ -/* Debug Core Register Selector Register Definitions */ +/* Debug SHAL Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ @@ -1184,7 +1184,7 @@ typedef struct @{ */ -/* Memory mapping of Core Hardware */ +/* Memory mapping of SHAL Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ @@ -1213,7 +1213,7 @@ typedef struct #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< SHAL Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ @@ -1221,7 +1221,7 @@ typedef struct #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< SHAL Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ diff --git a/Drivers/CMSIS/Include/core_cm3.h b/Drivers/CMSIS/Include/core_cm3.h index 74bff64..f8e30d8 100644 --- a/Drivers/CMSIS/Include/core_cm3.h +++ b/Drivers/CMSIS/Include/core_cm3.h @@ -1296,7 +1296,7 @@ typedef struct #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ -/* Debug Core Register Selector Register Definitions */ +/* Debug SHAL Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ @@ -1379,7 +1379,7 @@ typedef struct @{ */ -/* Memory mapping of Core Hardware */ +/* Memory mapping of SHAL Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ diff --git a/Drivers/CMSIS/Include/core_cm33.h b/Drivers/CMSIS/Include/core_cm33.h index 6cd2db7..edf7b08 100644 --- a/Drivers/CMSIS/Include/core_cm33.h +++ b/Drivers/CMSIS/Include/core_cm33.h @@ -1938,7 +1938,7 @@ typedef struct #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ -/* Debug Core Register Selector Register Definitions */ +/* Debug SHAL Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ @@ -2044,7 +2044,7 @@ typedef struct @{ */ -/* Memory mapping of Core Hardware */ +/* Memory mapping of SHAL Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ @@ -2078,7 +2078,7 @@ typedef struct #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< SHAL Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ @@ -2087,7 +2087,7 @@ typedef struct #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< SHAL Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ diff --git a/Drivers/CMSIS/Include/core_cm4.h b/Drivers/CMSIS/Include/core_cm4.h index 7d56873..81be06b 100644 --- a/Drivers/CMSIS/Include/core_cm4.h +++ b/Drivers/CMSIS/Include/core_cm4.h @@ -1467,7 +1467,7 @@ typedef struct #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ -/* Debug Core Register Selector Register Definitions */ +/* Debug SHAL Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ @@ -1550,7 +1550,7 @@ typedef struct @{ */ -/* Memory mapping of Core Hardware */ +/* Memory mapping of SHAL Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ diff --git a/Drivers/CMSIS/Include/core_cm7.h b/Drivers/CMSIS/Include/core_cm7.h index a14dc62..5a804c4 100644 --- a/Drivers/CMSIS/Include/core_cm7.h +++ b/Drivers/CMSIS/Include/core_cm7.h @@ -1675,7 +1675,7 @@ typedef struct #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ -/* Debug Core Register Selector Register Definitions */ +/* Debug SHAL Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ @@ -1758,7 +1758,7 @@ typedef struct @{ */ -/* Memory mapping of Core Hardware */ +/* Memory mapping of SHAL Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ diff --git a/Drivers/CMSIS/Include/core_sc000.h b/Drivers/CMSIS/Include/core_sc000.h index 9b67c92..998e11a 100644 --- a/Drivers/CMSIS/Include/core_sc000.h +++ b/Drivers/CMSIS/Include/core_sc000.h @@ -653,7 +653,7 @@ typedef struct @{ */ -/* Memory mapping of Core Hardware */ +/* Memory mapping of SHAL Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ diff --git a/Drivers/CMSIS/Include/core_sc300.h b/Drivers/CMSIS/Include/core_sc300.h index 3e8a471..4d0b1c8 100644 --- a/Drivers/CMSIS/Include/core_sc300.h +++ b/Drivers/CMSIS/Include/core_sc300.h @@ -1276,7 +1276,7 @@ typedef struct #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ -/* Debug Core Register Selector Register Definitions */ +/* Debug SHAL Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ @@ -1359,7 +1359,7 @@ typedef struct @{ */ -/* Memory mapping of Core Hardware */ +/* Memory mapping of SHAL Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ diff --git a/SHAL/Include/Core/SHAL_CORE.h b/SHAL/Include/Core/SHAL_CORE.h index 3a58a4e..fc358f0 100644 --- a/SHAL/Include/Core/SHAL_CORE.h +++ b/SHAL/Include/Core/SHAL_CORE.h @@ -8,7 +8,7 @@ #include -struct RCC_Peripheral { +struct SHAL_Peripheral { volatile uint32_t* reg; uint32_t bitmask; }; diff --git a/SHAL/Include/Peripheral/Timer/Reg/SHAL_TIM_REG.h b/SHAL/Include/Peripheral/Timer/Reg/SHAL_TIM_REG.h index 28d1c79..6842176 100644 --- a/SHAL/Include/Peripheral/Timer/Reg/SHAL_TIM_REG.h +++ b/SHAL/Include/Peripheral/Timer/Reg/SHAL_TIM_REG.h @@ -4,6 +4,8 @@ #include #include +#include "SHAL_CORE.h" + enum class Timer_Key { //For STM32F072 S_TIM1, S_TIM2, @@ -18,7 +20,7 @@ enum class Timer_Key { //For STM32F072 //Get timer peripheral struct including bus register, enable mask, timer mask -constexpr RCC_Peripheral getTimerRCC(Timer_Key t) { +constexpr SHAL_Peripheral getTimerRCC(Timer_Key t) { switch(t) { case Timer_Key::S_TIM1: return {&RCC->APB2ENR, RCC_APB2ENR_TIM1EN}; case Timer_Key::S_TIM2: return {&RCC->APB1ENR, RCC_APB1ENR_TIM2EN}; diff --git a/SHAL/Src/Reg/SHAL_TIM.cpp b/SHAL/Src/Reg/SHAL_TIM.cpp index 143cb8a..0e73ccf 100644 --- a/SHAL/Src/Reg/SHAL_TIM.cpp +++ b/SHAL/Src/Reg/SHAL_TIM.cpp @@ -2,11 +2,11 @@ // Created by Luca on 8/28/2025. // -#include "Core/Include/Timer/SHAL_TIM.h" +#include "SHAL_TIM.h" #include Timer::Timer(Timer_Key t) : timer(t), timer_reg(getTimerRegister(t)){ - RCC_Peripheral rcc = getTimerRCC(timer); + SHAL_Peripheral rcc = getTimerRCC(timer); *rcc.reg |= rcc.bitmask; }